The present invention relates to a drive circuit of an image display and a method of driving the same, and more particularly to a display, such as a liquid crystal display, a plasma display, and an EL display, which is suitable for displaying a gray scale of high picture quality with a simple circuit, and a method of driving the same.
As for a technology of displaying a gray scale in the prior art display, there is given JP-A-2-264294. A circuit portion and a performance chart which are directly related to the present invention are shown in FIG. 16A and FIG. 16B, respectively. In those figures, a reference numeral 100 designates an analog gate, a reference numeral 101 designates a holding capacitor, a reference numeral 102 designates an output buffer circuit, and a reference numeral 103 designates a level shifter.
As shown in this well known example, a step-like voltage As for determining brightness of a liquid crystal panel has voltage levels corresponding to only the number of gradations in brightness for being displayed on a display panel, e.g., 16 gradations.
That voltage is latched through the analog gate 100 in accordance with a timing signal Rpw(i). In this case, the gate 100 holds the voltage As at the rise of the timing signal Rpw(i). Since the pulse width of the above timing signal Rpw(i) is changed depending on the gradation information, the voltage at the analog gate 100 is changed. Thus, it is possible to display the gray scale.
In the above scheme, especially when the display panel is driven, the smaller circuit is available, as compared with any other scheme. However, the number of gradations in brightness become more than or equal to 16 and the duty ratio of the drive becomes small. That is, when the number of scanning lines increases, the drive time per gradation becomes short, and thus the analog gate 100 needs to be operated at high speed. As a result, not only the power consumption of the circuit increases, but also the noise from the timing signal Rpw(i) as the output signal of the level shifter 103 is superimposed on the output of the analog gate 100. As a result, the display of the display panel becomes nonuniform, and further a fixed noise pattern is generated.